
module ddr_pll_ck(

	input 	clk, 
	output 	clk1x, 
	output 	clkddrx
);
   
   wire        clk_buf_1x;
   wire        clk_buf_2x;
   wire        clk_buf_4x;
   
   
   //ddr_pll_clk1 ddr_pll_clk(.CLK_IN1(clk), .CLK_OUT1(clk_buf_1x), .CLK_OUT2(clk_buf_2x), .CLK_OUT3(clk_buf_4x));
   ddr_pll_clk ddr_pll_clk
 (// Clock in ports
  .CLK_IN1(clk),
  // Clock out ports
  .CLK_OUT1(clk_buf_1x),
  .CLK_OUT2(clk_buf_2x),
  .CLK_OUT3(clk_buf_4x)
 );
   

	assign clk1x = clk_buf_1x;
	assign clkddrx = clk_buf_1x;

   
endmodule
